1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having a ferro-electric capacitor.
2. Description of the Related Art
Ferro-electric memories (FeRAM) using ferro-electric capacitors are recently receiving a great deal of attention as nonvolatile semiconductor memories. As a ferro-electric memory, a “Series connected TC unit type ferro-electric RAM” has been proposed. In this memory, the two terminals of a ferro-electric capacitor (C) are connected to the source and drain of a cell transistor (T) to form a unit cell. A plurality of unit cells are connected in series to form the “Series connected TC unit type ferro-electric RAM”. As a ferro-electric memory read method, a “2T2C method” capable of ensuring a larger operation margin than a 1T1C method is receiving attention.
FIGS. 6 and 7 show the cell portion of a Series connected TC unit type ferro-electric RAM using the conventional 2T2C method.
In the conventional 2T2C method, adjacent bit lines serve as two complementary inputs of an operational sense amplifier. That is, as shown in FIGS. 6 and 7, when a bit line BL serves as the main input of an operational sense amplifier S/A, a bit line /BL adjacent to the bit line BL serves as an input complementary to the main input.
When the adjacent bit lines BL and /BL are used as the two complementary inputs, the layout around the sense amplifier S/A becomes simple. On the other hand, the adjacent bit lines BL and /BL interfere each other, resulting in a decrease in S/N ratio of a signal in a data read.
When offset-type cells are employed in this structure, they take an optimum cell layout as shown in FIG. 7 from the viewpoint of occupation area. More specifically, in the planar layout, memory cells connected to the adjacent bit lines BL and /BL are shifted in the horizontal direction on the drawing surface by a distance approximately corresponding to one cell, without being aligned. Due to this shift in the planar layout, two cell patterns which are paired and used for data comparison in the read differ.
For example, assume two adjacent memory cells connected to a single word line WL1. The two memory cells form a pair to be used for data comparison in the read. Of the two memory cells, one cell has an A-type pattern in which the upper electrode is connected to the bit line BL, and the lower electrode is connected to a plate line PL1. The other cell has a B-type pattern in which the lower electrode is connected to the bit line /BL, and the upper electrode is connected to a plate line PL2 (FIG. 3).
In a ferro-electric capacitor, generally, the hysteresis loop is sometimes asymmetrically shifted to the left or right side. This asymmetry is said to occur because, for example, the upper and lower electrodes are made of different materials, or the influence of damage caused during the ferro-electric memory manufacturing step differs between the interface of the upper electrode and that of the lower electrode. This phenomenon is generally called “initial imprint”.
When the hysteresis loop is asymmetrical, the signal amount changes between the A-type cell having the upper electrode connected to the bit line BL and the B-type cell having the lower electrode connected to the bit line /BL. More specifically, in read-accessing the ferro-electric memory cells by the 2T2C method, the output from the A-type cell and that from the B-type cell enter the complementary inputs of the operational sense amplifier. If the signal amount for the same data changes between the two cells, the margin in the data read becomes small.
As described above, the conventional ferro-electric memory which uses the adjacent bit lines BL and /BL as the two complementary inputs of the sense amplifier S/A has the following problems.
(1) Since the adjacent bit lines BL and /BL interfere each other, the S/N ratio of a signal in the data read degrades.
(2) Since the pair of cells connected to the bit lines BL and /BL have different layout patterns, the margin in the data read becomes small.
The problems (1) and (2) are preferably avoided because they may decrease the yield or reliability of ferro-electric memories.
A prior art related to this application is, for example, U.S. Pat. No. 4,922,459.